1. Field of the Invention
The present invention relates generally to improvements to computer systems and, more particularly but not by way of limitation, to apparatus for receiving data on both edges of a control signal.
2. Description of the Related Art
Computer systems commonly include one or more peripheral storage devices that are used to store and/or provide access to data. One common type of peripheral storage device is a hard disk drive. Other types of peripheral storage devices include tape drives, CD drives (both read-only and read/write), and DVD devices.
The most basic parts of a hard disk drive include at least one platter or "disk" that is rotated, an actuator that moves a transducer to various locations over the disk, and electrical circuitry that is used to write and read data to and from the disk. The disk drive also includes circuitry for encoding data so that data can be successfully retrieved from and written to the disk surface. The circuitry for encoding the data and circuitry that is used to perform the read and write operations on the disk are usually in a controller. The controller can be made as an integrated circuit placed within the hard disk drive. A disk drive microprocessor ("microprocessor") can be either embedded within or external to the controller integrated circuit.
The microprocessor controls most of the operations of the disk drive by configuring and monitoring the operation of the controller. For example, a host computer can initiate an operation by sending the controller a read command. The microprocessor recognizes the command and sets up registers in the controller to perform the read operation. The data is then read from the disk into a buffer. When a minimum amount of data is in the buffer the microprocessor sets up the controller to send the data from the buffer to the host.
The process of transferring data from a host to a hard disk typically involves two steps. First, the data is moved from a bus, connected to the host, to a data buffer within or coupled to the disc controller. Second, the data is transferred from the buffer and to the disk platter by magnetizing areas of the platter. The first step is generally referred to as the "external data transfer." The simplest buffer is just an array of memory cells within the controller. A buffer may also be an external Dynamic Random Access Memory (DRAM) external to the controller. The hard disk controller facilitates this transfer of data from a host bus to the buffer by using a buffer controller. The buffer controller includes logic to transfer data to and from the buffer. The separation between transfers from the host to the buffer and from the buffer to the platter is used to accommodate the fact that a sector is usually written or read as a single unit. In this manner the buffer is used to provide two data rates, one for data transfers from the system bus to the buffer, and the other for data transfers from the buffer to the physical platter.
The host system usually includes a host microprocessor used to control the operations of the host system. The host unit would typically include a peripheral device adapter such as an IDE disk controller to facilitate the interface between the host system and a storage device. The host system also includes memory used by the host during operation.
The external data transfer can be accomplished either as a synchronous or asynchronous transfer. Digital circuits in an electronic system are typically controlled by a common clock signal or by a plurality of clock signals derived from a common clock signal. Thus, the circuits are "synchronized" with respect to each other so that a signal generated by a first circuit in the system can be received by and clocked into other circuits in the system because the signals generated by the first circuit have a known phase relationship with respect to the common system clock signals. The known phase relationships typically do not exist for circuits that are controlled by independent clock signals. For example, peripheral components of a computer system often use independent clocks so that the peripheral component operates at a known frequency irrespective of the operating frequency of the computer system to which it is interconnected. Although the clock signals of a peripheral component and a computer system may have the same or similar frequencies, even very small differences in the clock frequencies cause the phase relationships between the clock signals to vary. Thus, the independent clock signals are "asynchronous" with respect to each other. Therefore, if a signal is generated by a circuit controlled by a clock which is asynchronous with the system clock, the signal cannot be simply provided to the circuits of the computer system and clocked by the clock signals derived from the system clock. Rather, the signal must be synchronized to the system clock before the signal can be applied to the circuits of the computer system. A synchronization would be accomplished by providing the same asynchronous signal received to the circuit output at a phase and rate used by a local clock. Thus, an asynchronous transfer of data as opposed to a synchronous transfer, involves the additional step of synchronizing the data phase to that used by the receiver. Therefore, a receiving unit in an asynchronous transfer mode has to provide two functions, one of data detection, and the other of a data synchronization. The synchronization of the data transferred is usually accomplished by sending asynchronous control signals along with the data to indicate the presence of valid data on a bus.
The ATA (AT-Attachment) or IDE interface is an example of a protocol that employs asynchronous data transfers. The ATA interface was originally defined as a standard for embedded fixed disk storage on IBM ATT.TM. compatible personal computers. "AT" stands for advanced technology which referred to the revolutionary, at the time, 16-bit bus used in the ATT.TM. computer. A DMA (Direct Memory Access) transfer is an example of an asynchronous data transfer within the ATA interface. For example, a DMA write operation would commence with the host writing an address to an ATA target register of the controller to specify the Logical Block Address (LBA) of the disk drive location where data is to be stored. The host then writes a command to a command register used by the controller to specify the operation to be performed. For example, a write operation command may be a "write DMA" command that is written to the command register. The microprocessor then sets up registers in the controller according to a firmware program stored on a ROM. The firmware includes the procedures followed by the microprocessor when processing commands in the command register. The procedure can vary depending on the transfer protocol used.
Once the host sets up the registers, the controller is ready to receive or provide data. For example, during a DMA write operation, the host bus controller sends data over by placing data on the data bus and asserting strobe signals that correspond to the data placed. The controller will detect the strobe signals asserted and receive data from the bus, one segment of data for every strobe detected. The controller also synchronizes the data to the controller clock. In this manner the host can send over as much data it wishes without regard to the clock phase of the target as long as each piece of data is accompanied by a strobe signal that complies with the bus specifications.
The rate of data transfer from the bus is governed by the bus specification, which defines required pulse widths and rates for the specific interface employed. The ATA-1 standard requires a minimum cyclc time of 480 ns for the write operation. Therefore, when using an ATA-1 bus which is 16 bit wide, a controller can receive data at a maximum rate of once every 480 ns or 4.1 MB/sec. The ATA-2 and the ATA-3 standards require a minimum cycle time of 120 ns which places a limit of 16.66 MB/sec on the data transfer rate. The standard can be enhanced as to increase the data transfer rate by reducing the minimum cycle time if termination devices and new cabling, such as PCI adapters, are used. However, the different cabling and termination devices are expensive and not easily installed in existing systems.
A new standard was adopted that is known as the Ultra ATA or Ultra DMA protocol. The new Ultra DMA protocol doubles the previous burst transfer rate of 16.6 MB per second to 33 MB per second by allowing data to be sent during both edges of the strobe signal. In this manner twice as much data is transferred per strobe cycle without changing the frequency of the strobe signal, and without the need for termination devices or different cabling.
To support the Ultra DMA protocol, hard disk controllers need to be able to receive data sent by the host on both edges of the strobe signal. ATA processors, for pre-Ultra DMA versions of the ATA standard, are configured to receive data on a single edge of the strobe signal. The clock rate for the controllers is set to enable the receiving of data on a single edge of a strobe, not both edges. Therefore, controllers have to employ faster clock rates to keep up with the faster stream of data coming in. The data from the bus has to be clocked-in fast enough before it is no longer valid. The circuit and method of the present invention offers an efficient and reliable method of receiving dual edge clocked data without the need for a faster controller clock rate.